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0V to 16V, Dual Hot-Swap Controller with 10-Bit
Current and Voltage Monitor and 4 LED Drivers
Power-Good Detection and PG_ Outputs
The PG_ output for a given channel is asserted when
the voltage at MON_ is between the undervoltage and
overvoltage critical limits. The status of the power-good
signals is maintained in register status3[3:0]. A value of
Table 30. status3 Register Format
1 in any of the pg[] bits indicates a power-good condi-
tion, regardless of the POL setting, which only affects the
PG_ output polarity. The open-drain PG_ output can be
configured for active-high or active-low status indication
by the state of the POL input (see Table 30).
Description:
Register Title:
Register Address:
Power-good status register; LATCH, POL, ALERT and Power Good bits
status3
0x34
R
—
bit 7
R
RETRY
bit 6
R
POL
bit 5
R/W
ALERT
bit 4
R
bit 3
R
bit 2
R
pg[1]
bit 1
R
pg[0]
bit 0
RESET
VALUE
0x00
The POL input sets the value of status3[5] , which is a
read-only bit; the state of the POL input can be changed
at any time during operation and the polarity of the PG_
The assertion of the PG_ output is delayed by a user-
selectable time delay of 50ms, 100ms, 200ms, or 400ms
(see Tables 31a and 31b).
outputs changes accordingly.
Table 31a. Power-Good Assertion Delay-Time Register Format
Description:
Register Title:
Register Address:
Power-good assertion delay-time register
pgdly
0x38
R
—
bit 7
R
—
bit 6
R
—
bit 5
R
—
bit 4
R/W
pgdly1
(CH1)
bit 3
R/W
pgdly0
(CH1)
bit 2
R/W
pgdly1
(CH0)
bit 1
R/W
pgdly0
(CH0)
bit 0
RESET
VALUE
0x00
Table 31b. Power-Good Assertion Delay
pgdly1 (CH_)
0
0
1
1
pgdly0 (CH_)
0
1
0
1
PG_ ASSERTION DELAY (ms)
50
100
200
400
______________________________________________________________________________________
27
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